Semiconductor memory device

ABSTRACT

An ECC circuit ( 103 ) is located between I/O terminals ( 104   0 - 104   7 ) and page buffers ( 102   0 - 102   7 ). The ECC circuit ( 103 ) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas ( 101   0 - 101   7 ), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas ( 101   0 - 101   7 ). The ECC circuit ( 103 ) allocates a set of 40 check bits (ECC) to an information bit length of 4224=528×8 to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area ( 101   j ).

CROSS REFERENCE TO RELATED APPLICATION

This application is based on and claims the benefit of prior JapanesePatent Application No. 2001-356571, filed on Nov. 21, 2001, the entirecontents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device such as aNAND-type flash memory, more particularly to a semiconductor memorydevice having an on-chip error correcting function.

2. Description of the Related Art

The NAND-type flash memory is known to deteriorate its cell propertythrough repeated operations of rewriting, and to vary data after it isleft for a long time. In order to improve the reliability of theNAND-type flash memory, such a semiconductor memory that contains an ECC(Error Correcting Code) circuit mounted on-chip for error detection andcorrection has been proposed in the art (for example, Japanese PatentApplication Laid-Open Nos. 2000-348497 and 2001-14888).

FIG. 21 is a block diagram briefly showing an arrangement of theconventional NAND-type flash memory with ECC circuits mounted thereon.

This memory comprises eight memory cell areas 1 ₀, 1 ₁, . . . , 1 ₇.Each of the memory cell areas 1 ₀, 1 ₁, . . . , 1 ₇ includes a pluralityof memory cells, not depicted, arrayed in a matrix. Data of 528 bits(=one page) can be written in and read out from 528 memory cellsconnected to a common word line through 528 bit lines at a time. Pagebuffers 2 ₀-2 ₇ are connected to the memory cell areas 1 ₀-1 ₇,respectively. Each page buffer can hold 528-bit write data and readdata. Between the page buffers 2 ₀-2 ₇ and I/O terminals 4 ₀-4 ₇ locatedcorresponding to the memory cell areas 1 ₀-1 ₇, ECC circuits 3 ₀-3 ₇ areprovided for the memory cell areas 1 ₀-1 ₇, respectively.

Each ECC circuit 3 ₀-3 ₇ has a coding function to add a certain bitnumber of check bits (ECC) to one page of information bits (528 bits) tobe stored in each memory cell area 1 ₀-1 ₇, and a decoding function todetect and correct a certain bit number of errors in the informationbits with the check bits added thereto. BCH (Bose-Chaudhuri-Hocquenghem)code is employed as an error correcting code that can correct aplurality of bit errors with a relatively small circuit scale. Betweenthe memory and external, data is read and written on a basis of 8 bitscorresponding to the number of memory cells. Data is fed bit by bit intoeach ECC circuit 3 ₀-3 ₇, and is circulated through and output from aninternal cyclic shift register bit by bit to execute coding anddecoding.

Operations of coding and decoding in the conventional ECC circuit 3 ₀-3₇ using BCH code will be described next.

The number of check bits in BCH code for correcting 2-bit errors anddetecting 3-bit errors is equal to 21 bits for 528 information bits. Forconvenience of description, a simple error detection and correctionsystem is described, which employs BCH code capable of correcting 2-biterrors and detecting 3-bit errors for the number of information bits,k=7, a code length, n=15, and the number of check bits, t=2.

In this case, a generating polynomial required for coding and decodingis given below as it is generally known: $\begin{matrix}{{{{Fundamental}\quad{Polynomial}\text{:}{F(X)}} = {X^{4} + X + 1}}{{\alpha\quad{Minimal}\quad{Polynomial}\text{:}\quad{M_{1}(x)}} = {X^{4} + X + 1}}{{\alpha^{3}\quad{Minimal}\quad{{Polynomial}:{M_{3}(x)}}} = {X^{4} + X^{3} + X^{2} + X + 1}}\begin{matrix}{{{Generating}\quad{Polynomial}\text{:}G\quad(x)}\quad = {M_{1}M_{3}}} \\{= {X^{8} + X^{7} + X^{6} + X^{4} + 1}}\end{matrix}} & (1)\end{matrix}$(1) Coder

FIG. 22 is a block diagram showing a coder 10 functionally configuredinside the conventional ECC circuit 3 i (i=0, 1, . . . , or 7). Thecoder 10 comprises a shift register 11 consisting of registers D₇, D₆,D₅, D₄, D₃, D₂, D₁, D₀, XOR circuits 12 ₁, 12 ₂, 12 ₃, 12 ₄ for modulo-2operations, and circuit changing switches SW1, SW2.

An operation for moving the shift register 11 once corresponds tomultiplying each value in the shift register 11 by X. A value of datastored in the shift register 11 can be expressed by:a₀X⁰+a₁X¹+a₂X²+a₃X³+a₄X⁴+a₅X⁵+a₆X⁶+a₇X⁷  (2)where a_(i) denotes a value stored in a register D_(i), and a_(i)=0 or 1(i=0-7). When this is shifted once, the following is obtained:a₀X¹+a₁X²+a₂X³+a₃X⁴+a₄X⁵+a₅X⁶+a₆X⁷+a₇X⁸  (3)

From the generating polynomial G(x) given by Expression (1), a relationof X⁸=X⁷+X⁶+X⁴+1 is derived. Therefore, Expression (3) can berepresented by:a₇X⁰+a₀X¹+a₁X²+a₂X³+(a₃+a₇)X⁴+a₄X^(5+(a) ₅+a₇)X⁶+(a₆+a₇)X⁷  (4)This corresponds to shifting each bit; storing the value a₇ of theregister D₇ into the register D₀; adding the values a₃, a₇ of theregisters D₃, D₇ at the XOR circuit 12 ₁ and storing the sum into theregister D₄; adding the values a₅+a₇ of the registers D₅, D₇ at the XORcircuit 12 ₂ and storing the sum into the register D₆; and adding thevalues a₆+a₇ of the registers D₆, D₇ at the XOR circuit 12 ₃ and storingthe sum into the register D₇.

On coding, the switches SW1, SW2 are first connected to ON sides toenter input data (information bits) I₀, I₁, I₂, I₃, I₄, I₅, I₆ (I₀-I₆=0or 1) bit by bit from external through the I/O terminal 4 i. Every timeone bit of the input data I₀-I₆ enters, the shift register 11 operatesonce. As the switch SW1 is kept ON during the input data I₀-I₆ entering,the data is output bit by bit to the page buffer 2 i as it is. At thesame time, the input data I₀-I₆ is added to the value a₇ of the registerD₇ at the XOR circuit 12 ₁ and the sum is stored in turn into the shiftregister 11. After completion of the input data I₀-I₆ entered into thepage buffer 2 i, check bits I₇, I₈, I₉, I₁₀, I₁₁, I₁₂, I₁₃, I₁₄ arestored inside the registers D₇, D₆, D₅, D₄, D₃, D₂, D₁, D₀ of the shiftregister 11, respectively. The switches SW1, SW2 are then connected toOFF sides and, every time the shift register 11 operates, the check bitsI₇-I₁₄ are output serially to the page buffer 2 i through the switchSW1. The information bits and check bits stored in the page buffer 2 iare written into the memory cell area 1 i. At the same time, the valuein the shift register 11 is reset.

(2) Decoder

A decoder is described next. The decoder comprises syndromecomputational circuits and an error position detector. In the case of2-bit error detection, two syndromes S₁, S₃ are required for decoding.These syndromes can be derived from the minimal polynomial M₁(x)=X⁴+X+1as it is known. FIG. 23 specifically shows (A) a conventional S₁syndrome computational circuit 20 and (B) a conventional S₃ syndromecomputational circuit 30.

Based on the minimal polynomial M₁(x), the S₁ syndrome computationalcircuit 20 in FIG. 23A comprises a shift register 21 consisting ofregisters D₃, D₂, D₁, D₀, and XOR circuits 22 ₁, 22 ₂. An operation formoving the shift register 21 once corresponds to multiplying a value inthe shift register 21 by X. The value stored in the shift register 21can be expressed by:a₀X⁰+a₁X¹+a₂X²+a₃X³  (5)where a_(i) denotes a value stored in a register D_(i), and a_(i)=0 or 1(i=0-3). When this is shifted once, the following is obtained:a₀X¹+a₁X²+a₂X³+a₃X⁴  (6)From the α minimal polynomial M₁(x), a relation of X⁴=X+1 is derived.Accordingly:a₃X⁰+(a₀+a₃)X¹+a₁X²+a₂X³  (7)This corresponds to shifting each bit; storing the value a₃ of theregister D₃ into the register D₀; and adding the values a₀, a₃ of theregisters D₀, D₃ at the XOR circuit 12 ₂ and storing the sum into theregister D₁. The information bits I₀-I₆ and check bits I₇-I₁₄ are fed inthis order into the S₁ syndrome computational circuit 20 bit by bit. Theshift register 21 operates once every time one bit enters. After allbits I₀-I₁₄ enter, the syndrome S₁ is generated in the shift register 21(D₀-D₃).

Similar to the S₁ syndrome computational circuit 20, the S₃ syndromecomputational circuit 30 in FIG. 23B comprises a shift register 31consisting of registers D₃, D₂, D₁, D₀, and XOR circuits 32 ₁, 32 ₂, 32₃, 32 ₄. It is configured by the X³ circuit of the minimal polynomialM₁(x). In the S₃ syndrome computational circuit 30, an operation formoving the shift register 31 once corresponds to multiplying a value inthe shift register 31 by X³. The value stored in the shift register 31is expressed by Expression (5). When it is multiplied by X³, thefollowing is given:a₀X³+a₁X⁴+a₂X⁵+a₃X⁶  (8)From the α minimal polynomial M₁(x), a relation of X⁴=X+1 is derived.Accordingly:a₁X⁰+(a₁+a₂)X¹+(a₂+a₃)X²+(a₀+a₃)X³  (9)This corresponds to shifting each bit; storing the value a₁ of theregister D₁ into the register D₀; adding the values a₁, a₂ of theregisters D₁, D₂ at the XOR circuit 32 ₂ and storing the sum into theregister D₁; adding the values a₂, a₃ of the registers D₂, D₃ at the XORcircuit 32 ₃ and storing the sum into the register D₂; and adding thevalues a₀, a₃ of the registers D₀, D₃ at the XOR circuit 324 and storingthe sum into the register D₃. The information bits I₀-I₆ and check bitsI₇-I₁₄ stored in the memory cells are also fed in this order into the S₃syndrome computational circuit 30 bit by bit. The shift register 31operates once every time one bit enters. After all bits I₀-I₁₄ enter,the syndrome S₃ is generated in the shift register 31 (D₀-D₃).

FIG. 24 is a flowchart showing an algorithm for decoding. The S₁, S₃syndrome computational circuits 20, 30 compute syndromes S₁, S₃ firstbased on the information bits and check bits read out from the memorycell area 1 i (step S1). If the syndromes S₁, S₃ are S1=S3=0, it isdetermined errorless, and the read-out information bits are output asthey are (steps S2, S3, S4). If only one of the syndromes S₁, S₃ isequal to 0, it is determined uncorrectable, and the data is output as itis (steps S2, S3, S5, S6, S7). If S₁≠0 and S₃≠0, computations areexecuted to derive σ₁=S₁ ² and σ₂=S₁ ³+S₃ (steps S2, S6, S8). If σ₂=0(step S9), it can be found that a 1-bit error is present, and 1-bitcorrected data is output (step S10). If σ₂≠0 (step S9), it can be foundthat 2-bit errors are present, and 2-bit corrected data is output (stepS11).

The position of the error bit can be found by assigning Z=α^(I) (I=0, 1,2, 3, 4, 5, 6) in turn to an error position polynomial σ(Z) representedby Expression (10) as it is known generally. The position of the errorcan be indicated by i that holds σ(α^(I))=0.σ(Z)=S ₁+σ₁ ×Z+σ ₂ ×Z ²  (10)

An arrangement of the error position detector is shown in FIGS. 25 and26, which is configured based on such the point. FIG. 25 shows a firstarithmetic section 40 a that computes and stores S₁, σ and σ₂. FIG. 26shows a second arithmetic section 40 b that executes the operation ofExpression (10) based on the operated result from the first arithmeticsection 40 a and outputs a detection signal to indicate the errorposition in the data. As shown in FIG. 25, the first arithmetic section40 a comprises a shift register 41, an X arithmetic circuit 42, and anX² arithmetic circuit 43. A shift register 41 a stores the syndrome S₁,and shift registers 42 a and 43 a store the operated results, σ₁=S₁ ²and σ₂=S₁ ³+S₃. It is assumed that the shift register 42 a has a valueof:a₀X⁰+a₁X¹+a₂X²+a₃X³  (11)where a_(i) denotes a value stored in a register D_(i), and a_(i)=0 or 1(i=0-3). As the X arithmetic circuit 42 multiplies it by X, the value ofthe shift register 42 a comes to:a₀X¹+a₁X²+a₂X³+a₃X⁴  (12)From the α minimal polynomial M₁(x), a relation of X⁴=X+1 is present.Accordingly, Expression (12) yields:a₃X⁰+(a₀+a₃)X¹+a₁X²+a₂X³  (13)This corresponds to shifting each bit; storing the value a₃ of theregister D₃ into the register D₀; and adding the values a₀, a₃ of theregisters D₀, D₃ at the XOR circuit 42 ₂ and storing the sum into theregister D₁.

The X² arithmetic circuit 43 multiplies the value of the shift register43 a by X². Therefore, when the value indicated by Expression (11) isstored in the shift register 43 a, and it is multiplied by X², the valueof the shift register 43 a comes to:a₀X²+a₁X³+a₂X⁴+a₃X⁵  (14)From the α minimal polynomial M₁(x), a relation of X⁴=X+1 is present.Accordingly, Expression (14) yields:a₂X⁰+(a₂+a₃)X¹+(a₀+a₃)X²+a₁X³  (15)This corresponds to shifting each bit; storing the value a₂ of theregister E₂ into the register E₀; storing the value a₁ of the registerE₁ into the register E₃; adding the values a₂, a₃ of the registers E₂,E₃ at the XOR circuit 43 b ₁ and storing the sum into the register E₁;and adding the values a₀, a₃ of the registers E₀, E₃ at the XOR circuit43 b ₂ and storing the sum into the register E₂.

When 1-bit data I₀-I₆ is output, one shift operation of the shiftregisters 41 a, 42 a, 43 a multiplies the term of σ₁ by Z in the Xarithmetic section 42 and the term of σ₂ by Z² in the X² arithmeticsection 43. The NAND-type flash memory operates the shift registers 41a, 42 a, 43 a in synchronization with the toggle signal that is employedto output the information bits stored in the memory cell to outside thechip. In the second arithmetic circuit 40 b, the result from theoperation through an XOR circuit 44 and an NOR gate 45 exhibits ‘1’ atthe error position. This output is employed to invert the correspondingdata Ii to detect and correct the error.

Thus, in the conventional ECC circuit that employs BCH code, one shiftand computation per 1-bit input is the basic operation. The NAND-typeflash memory receives parallel data input from external on a basis of8-I/O or 16-I/O per address. Therefore, it is required to correct anerror per I/O or compute 8 or 16 times during the one input. The 8 or16-time computation during the one input needs a fast operation for thispart, which can not be achieved practically because a special process isrequired, for example.

Therefore, an ECC circuit 3 i is provided for each memory cell area 1 i(each I/O) in the art to correct errors on a basis of each memory cellarea 1 i. The NAND-type flash memory reads and programs data per page(528 bytes). If it intends to correct 2-bit errors and detect 3-biterrors per I/0, it requires 21 check bits for 528 information bits,21×8=168 extra check bits in total for the entire chip. This is aninhibit factor for improving the chip integration density.

The present invention has been made in consideration of such the problemand accordingly has an object to provide a semiconductor memory devicecapable of reducing the number of check bits relative to the number ofinformation bits to improve a chip integration density.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the invention, a semiconductor memory devicecomprises a plurality of memory cell areas, each of which includes aplurality of memory cells arrayed in a matrix and has a data I/Oportion; a plurality of buffers, each of which is located on the dataI/O portion at each memory cell area to temporarily store data to bewritten into the memory cell area and data read out from the memory cellarea; a plurality of I/O terminals, each of which is configured toreceive the data to be written into the memory cell area from externaland output the data read out from the memory cell area to external; andan error correction circuit located between the plurality of I/Oterminals and the plurality of buffers, the error correction circuitincludes a coder configured to generate check bits for error correctingand to attach the check bits to the data to be written into the memorycell area and a decoder configured to process for error correcting thedata read out from the memory cell area with the generated check bits,the error correction circuit operates to allocate a set of check bits toan information bit length of M×N (N denotes an integer of two or more)to execute at least one of coding and decoding by parallel processingN-bit data, where M denotes the number of bits in a unit of data to bewritten into and read out from the memory cell area.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more fully understood from the followingdetailed description with reference to the accompanying drawings, inwhich:

FIG. 1 is a block diagram showing an arrangement of a coder for use inan ECC circuit mounted on a flash memory according to a first embodimentof the present invention;

FIG. 2 is a block diagram showing an arrangement of a shift register foruse in the coder;

FIG. 3 is a truth table of an XOR circuit for use in the coder;

FIGS. 4A and AB are block diagrams showing syndrome computationalcircuits in a decoder for use in the ECC circuit;

FIG. 5 is a block diagram showing a first arithmetic section containedin an error position detector for use in the decoder;

FIG. 6 is a block diagram showing a second arithmetic section containedin the error position detector;

FIG. 7 is a block diagram showing a NAND-type flash memory according toa second embodiment of the present invention;

FIG. 8 is a circuit diagram showing an arrangement of a memory cell areain the flash memory;

FIG. 9 is a block diagram showing an ECC circuit in the flash memory;

FIG. 10 shows registers contained in an arithmetic logic circuit oncoding in the ECC circuit;

FIG. 11 is a flowchart showing an operation of coding in the coder;

FIG. 12 is a timing chart on coding;

FIG. 13 shows registers contained in an arithmetic logic circuit fordecoding in the ECC circuit;

FIG. 14 is a flowchart showing an operation of decoding;

FIG. 15 is a block diagram of an error position detector in the ECCcircuit;

FIG. 16 is a flowchart showing an algorithm for computing each term inan error position polynomial in the error position detector;

FIGS. 17A, 17B and 17C are block diagrams of a Galois arithmetic circuitin the ECC circuit;

FIG. 18 shows a second arithmetic section in the error positiondetector;

FIG. 19 is a block diagram of another error position detector in the ECCcircuit;

FIGS. 20A and 20B are timing charts on decoding in the ECC circuit;

FIG. 21 is a block diagram showing an arrangement of the NAND-type flashmemory with conventional ECC circuits mounted thereon;

FIG. 22 is a block diagram showing a coder in the conventional ECCcircuit;

FIGS. 23A and 23B are block diagrams showing conventional syndromecomputational circuits;

FIG. 24 is a flowchart showing a decoding algorithm in the conventionalECC circuit;

FIG. 25 is a block diagram showing a first arithmetic section containedin an error position detector in the conventional ECC circuit; and

FIG. 26 is a block diagram showing a second arithmetic section containedin the error position detector in the conventional ECC circuit.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below withreference to the drawings.

(1) First Embodiment

In order to provide an understanding of the present invention, 2-biterror correction is exemplified as a first embodiment with the number ofinformation bits, k=7, a code length, n=15, and the number of correctionbits, t=2.

(1-1) Coder

When input data I₀ enters the conventional coder 11 shown in FIG. 22,the input data I₀ is added at the XOR circuit 124 to the term of X⁷ inthe coder, then multiplied by X. Each register 11 in the coder 10 in theinitial state has a value of 0, which is referred to as (0).Accordingly:(0+I₀X⁷)X  (17)When next input data I₁ enters the coder 10, the input data I₁ is addedto the term of X⁷ in the coder 10, then multiplied by X to yield:((0+I₀X⁷)X+I₁X⁷)X  (18)

When next input data I₂ enters the coder 10, the input data I₂ is addedto the term of X⁷ in the coder 10, then multiplied by X to yield:(((0+I ₀ X ⁷)X+I ₁ X ⁷)X+I ₂ X ⁷)X  (19)

Similarly, after input data, up to I₆, enters the coder 10, thefollowing is given:(((((((0+I₀X⁷)X+I₁X⁷)X+I₂X⁷)X+I₃X⁷)X+I₄X⁷)X+I₅X⁷)X+I₆X⁷)X  (20)This expression can be altered in:((((0+I₀X⁷)X+I₁X⁶)X²+I₂X⁷)X+I₃X⁶)X²+I₄X⁷)X²+I₅X⁶)X²+I₆X⁷)X  (21)This means that the pieces of input data I₀, I₁ are added to the termsof X⁷, X⁶ in the coder 10, respectively, then multiplied by X².Thereafter, the pieces of input data I², I³ are added to the terms ofX⁷, X⁶ in the coder 10, respectively, then multiplied by X². Finally thepieces of input data I₄, I₅ are added to the terms of X⁷, X⁶ in thecoder 10, respectively, then multiplied by X². In a word, one operationof the shift register 11 after two bits input can multiply the data byX². As for the last data I₆, however, one bit input multiplies it by Xas is in the art.

When the value of the shift register 11 represented by Expression (2) ismultiplied by X², it comes to:a₀X²+a₁X³+a₂X⁴+a₃X⁵+a₄X⁶+a₅X⁷+a₆X⁸+a₇X⁹  (22)From the generating polynomial G(x) given by Expression (1), a relationof X⁸=X⁷+X⁶+X⁴+1 is derived. Therefore, Expression (21) yields:(a₆+a₇)X⁰+a₇X¹+a₀X²+a₁X³+(a₂+a₆+a₇)X⁴+(a₃+a₇)X⁵+(a₄+a₆+a₇)X⁶+(a₅+a₆)X⁷  (23)

FIG. 1 is a block diagram showing a circuit arrangement of a coder 50according to the present embodiment that specifically configuresExpression (23).

The coder 50 comprises a shift register 51 consisting of registers D₇,D₆, D₅, D₄, D₃, D₂, D₁, D₀, XOR circuits 521, 522, 523, 524, 525, 526,527, and four switches SW11, SW12, SW21, SW22 for changing input dataand output data. The shift register 51 includes four-stage transfergates 51 a and other necessary gate circuits 51 b as shown in FIG. 2. Inthe transfer gates 51 a, a reset signal RSTn is employed to reset thecontents of data and a clock signal CLK to synchronously transfer 1-bitdata from an input terminal IN to an output terminal OUT. An XOR circuit52 applies a modulo-2 operation to data input from input terminals IN1,IN2, as shown in FIG. 3, and output the result from an output terminalOUT.

Based on Expression (23), the coder 50 through one shift operationperforms: adding the values a₆, a₇ of the registers D₆, D₇ at the XORgate 526 and storing the sum into the register D₀; storing the value a₇of the register D₇ into the register D₁; storing the value a₀ of theregister D₀ into the register D₂; storing the value a₁ of the registerD₁ into the register D₃; adding the values a₂, a₆, a₇ of the registersD₂, D₆, D₇ at the XOR gates 52 ₁, 52 ₆ and storing the sum into theregister D₄; adding the values a₃, a₇ of the registers D₃, D₇ at the XORgate 522 and storing the sum into the register D₅; adding the values a₄,a₆, a₇ of the registers D₄, D₆, D₇ at the XOR gates 52 ₃, 52 ₆ andstoring the sum into the register D₆; and adding the values a₅, a₆ ofthe registers D₅, D₆ at the XOR gate 52 ₅ and storing the sum into theregister D₇.

The pieces of input data (information bits) I₀, I₁, I₂, I₃, I₄, I₅, I₆,given from external to be written into the memory, are divided into two:input data I₀, I₂, I₄ and input data I₁, I₃, I₅. The input data I₀, I₂,I₄ is fed to ON sides of the switches SW11, SW21. The input data I₁, I₃,I₅ is fed to ON sides of the switches SW12, SW22. The pieces of inputdata are fed by two bits in parallel in an order of (I₀, I₁), (I₂, I₃),(I₄, I₅). After the input, the shift register 51 operates once. As theshift register 51 is connected to every other one, one shift operationmultiplies the data by X². While the pieces of data (I₀, I₁), (I₂, I₃),(I₄, I₅) enter, the switches SW11, SW12, SW21, SW22 are all kept ON toallow these pieces of data to output by two bits in parallel as theyare. At the same time, the data I₀, I₂, I₄ is added to the value a₇ ofthe register D₇ at the XOR circuit 52 ₇ and sequentially stored in theshift register 51. The data I₁, I₃, I₅ is added to the value a₇ of theregister D₇ at the XOR circuit 52 ₄ and sequentially stored in the shiftregister 51. As the last I₆ of the input data is 1-bit input, theconnection is switched to the same as in the conventional coder 10 shownin FIG. 22. Such the switching is required because k=7 is selected asthe number of information bits. After completion of input of the dataI₀, I₁, I₂, I₃, I₄, I₅, I₆, check bits I₇, I₈, I₉, I₁₀, I₁₁, I₁₂, I₁₃,I₁₄ are stored inside the registers D₇, D₆, D₅, D₄, D₃, D₂, D₁, D₀ inthe shift register 51, respectively. The switches SW11, SW12, SW21, SW22are then all connected to OFF sides. Thus, every time the shift register51 operates, the check bits I₇, I₉, I₁₁, I₁₃ are fed to the output ofthe switch SW11 and the check bits I₈, I₁₀, I₁₂, I₁₄ to the output ofthe switch SW12. At the same time, the value in the shift register 51 isreset. This allows check bits to be generated through 2-bit inputparallel processing.

(1-2) Decoder

{circle around (1)} S₁ Syndrome Computational Circuit

In the conventional S₁ syndrome computational circuit 20 of FIG. 23A,the value in the S₁ syndrome computational circuit 20 is firstmultiplied by X, then the input data I₀ is added to the term of X⁰ atthe XOR circuit 22 ₁. The shift register 21 in the S₁ syndromecomputational circuit 20 in the initial state has a value of 0, which isreferred to as (0). Accordingly:0×X+I₀  (24)After the value in the S₁ syndrome computational circuit 20 ismultiplied by X, the input data I₁ is added to the term of X₀.Accordingly:(0×X+I₀)X+I₁  (25)

Subsequently, after the value in the S₁ syndrome computational circuit20 is multiplied by X, the input data I₂ is added to the term of X⁰.Accordingly:((0×X+I₀)X+I₁)X+I₂  (26)When the input data, up to I₁₄, enters the S₁ syndrome computationalcircuit 20, the following is given:(((((((((((((0×X+I₀)X+I₁)X+I₂)X+I₃)X+I₄)X+I₅)X+I₆)X+I₇)X+I₈)X+I₉)X+I₁₀)X+I₁₁)X+I₁₂)X+I₁₃)X+I₁₄  (27)The expression can be altered in:(((((((0×X²+I₀X+I₁)X²+I₂X+I₃)X²+I₄X+I₅)X²+I₆X+I₇)X²+I₈X+I₉)X²+I₁₀X+I₁₁)X²+I₁₂X+I₁₃)X+I₁₄  (28)This means that after the value in the S₁ syndrome computational circuit20 is multiplied by X², the input data I₀ is added to the term of X¹,and the input data I₁ to the term of X⁰. Then, after the value in the S₁syndrome computational circuit 20 is multiplied by X², the input data I₂is added to the term of X¹, and the input data I₃ to the term of X⁰.Next, after the value in the S₁ syndrome computational circuit 20 ismultiplied by X², the input data I₄ is added to the term of X¹, and theinput data I₅ to the term of X⁰. In a word, one operation of the shiftregister multiplies the data by X², then 2-bit data enters. Finally,after the value in the S₁ syndrome computational circuit 20 ismultiplied by X, the input data I₁₄ is added to the term of X₀ by 1-bitinput.

When the value of the shift register 21, expressed by Expression (5), ismultiplied by X², the following is given:a₀X²+a₁X³+a₂X⁴+a₃X⁵  (29)From, the a minimal polynomial M₁(x), a relation of X⁴=X+1 is derived.Accordingly:a₂X⁰+(a₂+a₃)X¹+(a₀+a₃)X²+a₁X³  (30)

FIG. 4A is a block diagram showing a circuit arrangement of an S₁syndrome computational circuit 60 according to the present embodimentthat specifically configures Expression (30).

The S₁ syndrome computational circuit 60 comprises a shift register 61consisting of registers D₀, D₁, D₂, D₃, and XOR circuits 62 ₁, 62 ₂, 62₃, 62 ₄.

Based on Expression (30), the S₁ syndrome computational circuit 60through one shift operation performs: storing the value a₂ of theregister D₂ into the register D₀; adding the values a₂, a₃ of theregisters D₂, D₃ at the XOR circuit 62 ₂ and storing the sum into theregister D₁; adding the values a₀, a₃ of the registers D₀, D₃ at the XORcircuit 62 ₄ and storing the sum into the register D₂; and storing thevalue a₁ of the register D₁ into the register D₃.

The information bits I₀, I₁, I₂, I₃, I₄, I₅, I₆ and check bits I₇, I₈,I₉, I₁₀, I₁₁, I₁₂, I₁₃, I₁₄ read out from the memory cell area, notdepicted, are divided into I₀, I₂, I₄, I₆, I₅, I₁₀, I₁₂, I₁₄ and I₁, I₃,I₅, I₇, I₉, I₁₁, I₁₃ and fed by two bits in parallel in an order of (I₀,I₁), (I₂, I₃), (I₄, I₅), . . . to the S₁ syndrome computational circuit60. After the input, the shift register 61 operates once. As the shiftregister 61 is connected to every other one, one shift operationmultiplies the data by X². The data I₀, I₂, I₄, . . . , I₁₄ is added atthe XOR circuit 62 ₃ to the output, a₂+a₃, from the XOR circuit 62 ₂ andthe sum is stored in the register D₁. The data I₁, I₃, I₅, . . . , I₁₃is added at the XOR circuit 62 ₁ to the value a₂ of the register D₂ andthe sum is stored in the register D₀. As the last I₆ of the informationbits is 1-bit input, the connection is switched to the same as in thecircuit of FIG. 23. Alternatively, it is possible to input I₁₅=0 to theS₁ syndrome computational circuit 60 and, after a shift operation,multiply the shift register by X⁻¹. This allows 2-bit input parallelprocessing to be performed.

{circle around (2)} S₃ Syndrome Computational Circuit

A S₃ syndrome computational circuit 70 in FIG. 4B is described next. Inthe conventional S₃ syndrome computational circuit 30 in FIG. 23A, thevalue in the S₃ syndrome computational circuit 30 is first multiplied byX³, then the input data I₀ is added to the term of X₀ at the XOR circuit32 ₁. The shift register 31 in the S₃ syndrome computational circuit 30in the initial state has a value of 0, which is referred to as (0).Accordingly:0×X³+I₀  (31)After the value in the S₃ syndrome computational circuit 30 ismultiplied by X³, the input data I₁ is added to the term of X₀.Accordingly:(0×X³+I₀)X+I₁  (32)Subsequently, after the value in the S₃ syndrome computational circuit30 is multiplied by X³, the input data I₂ is added to the term of X₀.Accordingly:((0×X³+I₀)X³+I₁)X³ +I ₂  (33)When the input data, up to I₁₄, enters the S₃ syndrome computationalcircuit 30, the following is given:(((((0×X³+I₀)X³+I₁)X³+I₂)X³+I₃)X³+I₄)X³+I₅)X³+I₆)X³+I₇)X³+I₈)X³+I₉)X³+I₁₀)X³+I₁₁)X³+I₁₂)X³+I₁₃)X³+I₁₄  (34)The expression can be altered in:(((((0×X⁶+I₀X³+I₁)X⁶+I₂X³+I₃)X⁶+I₄X³+I₅)X⁶+I₆X³+I₇)X⁶+I₈X³+I₉)X⁶+I₁₀X³+I₁₁)X⁶+I₁₂X³+I₁₃)X³+I₁₄  (35)This means that after the value in the S₃ syndrome computational circuit30 is multiplied by X⁶, the input data I₀ is added to the term of X³,and the input data I₁ to the term of X⁰. Then, after the value in the S₃syndrome computational circuit 30 is multiplied by X⁶, the input data I₂is added to the term of X³, and the input data I₃ to the term of X⁰.Next, after the value in the S₃ syndrome computational circuit 30 ismultiplied by X⁶, the input data I₄ is added to the term of X³, and theinput data I₅ to the term of X⁰. In a word, one operation of the shiftregister multiplies the data by X⁶, then 2-bit data is input. Finally,after the value in the S₃ syndrome computational circuit 30 ismultiplied by X³, the input data I₁₄ is added to the term of X₀ by 1-bitinput.

When the value of the shift register 31, expressed by Expression (5), ismultiplied by X⁶, the following is given:a₀X⁶+a₁X⁷+a₂X⁸+a₃X⁹  (36)From the α minimal polynomial M₁(x), a relation of X⁴=X+1 is derived.Accordingly:(a₁+a₂)X⁰+(a₁+a₃)X¹+(a₀+a₂)X²+(a₀+a_(l)+a₃)X³  (37)

FIG. 4B is a block diagram showing a circuit arrangement of the S₃syndrome computational circuit 70 according to the present embodimentthat specifically configures Expression (37).

The S₃ syndrome computational circuit 70 comprises a shift register 71consisting of registers D₀, D₁, D₂, D₃, and XOR circuits 72 ₁, 72 ₂, 72₃, 72 ₄, 72 ₅, 72 ₆.

Based on Expression (37), the S₃ syndrome computational circuit 70through one shift operation performs: adding the values a₁, a₂ of theregisters D₁, D₂ at the XOR circuit 72 ₂ and storing the sum into theregister D₀; adding the values a₁, a₃ of the registers D₁, D₃ at the XORcircuit 72 ₆ and storing the sum into the register D₁; adding the valuesa₀, a₂ of the registers D₀, D₂ at the XOR circuit 72 ₄ and storing thesum into the register D₂; and adding the values a₀, a₁, a₃ of theregisters D₀, D₁, D₃ at the XOR circuits 72 ₅, 72 ₆ and storing the suminto the register D₃.

The information bits I₀, I₁, I₂, I₃, I₄, I₅, I₆ and check bits I₇, I₈,I₉, I₁₀, I₁₁, I₁₂, I₁₃, I₁₄ read out from the memory cell area, notdepicted, are divided into I₀, I₂, I₄, I₆, I₈, I₁₀, I₁₂, I₁₄ and I₁, I₃,I₅, I₇, I₉, I₁₁, I₁₃ and fed by two bits in parallel in an order of (I₀,I₁), (I₂, I₃), (I₄, I₅), . . . to the S₃ syndrome computational circuit70. After the input, the shift register 71 operates once. The data I₀,I₂, I₄, . . . , I₁₄ is added at the XOR circuit 72 ₃ to the output,a₁+a₃, from the XOR circuit 72 ₆ and the sum is stored in the registerD₁. The data I₁, I₃, I₅, . . . , I₁₃ is added to the output, a₁+a₂, fromthe XOR circuit 72 ₁ at the XOR circuit 72 ₂ and the sum is stored inthe register D₀. As the last I₆ of the information bits is 1-bit input,the connection is switched to the same as in the S₃ syndromecomputational circuit 30 of FIG. 23. Alternatively, it is possible toinput I₁₅=0 ^(to the S) ₃ syndrome computational circuit 70 and, after ashift operation, multiply the shift register by X⁻³. This allows 2-bitinput parallel processing to be performed.

{circle around (3)} Error Position Detector

An error position detector is described next. In the error positiondetector in the present embodiment, the S₁, S₃ syndrome computationalcircuits 60, 70 perform one shift operation corresponding to theconventional two shift operations. Therefore, the error positiondetector performs an arithmetic also corresponding to the conventionaltwo shift operations. The error position polynomial (10) is alsorepresented by:σ(Z)=S ₁+σ₁ ×Z ²+σ₂ ×Z ⁴  (38)

FIGS. 5 and 6 show an arrangement of the error position detectorconfigured based on Expression (38).

The error position detector 80 comprises a first arithmetic section 80 a(FIG. 5) that computes and stores S₁, σ₁ and σ₂, and a second arithmeticsection 80 b that detects a data error position based on Expression (38)and outputs a detection signal. As shown in FIG. 5, the first arithmeticsection 80 a comprises a shift register 81, an X² arithmetic circuit 82,and an X⁴ arithmetic circuit 83. A shift register 81 a stores thesyndrome S₁ as the initial state, and shift registers 82 a, 83 a storethe operated results, σ₁=S₁ ² and σ=S₁ ³+S₃, as the initial states. Theerror position detector 80 executes error detection in synchronizationwith every other data I₀, I₂, I₄, I₆ among the output data I₀, I₁, I₂,I₃, I₄, I₅, I₆. It operates the shift registers 81 a, 82 a, 83 a once tomultiply the term of σ₁ by Z² in the X² arithmetic circuit 82, and theterm of σ₂ by Z⁴ in the X⁴ arithmetic circuit 83. If any error ispresent, then σ=0.

The X² arithmetic circuit 82 has the same arrangement as the X²arithmetic circuit 43 in FIG. 25: the shift register 43 a corresponds tothe shift register 82 a; and the XOR circuits 43 b ₁, 43 b ₂ to the XORcircuits 82 b ₁, 82 b ₂. Therefore, detailed arrangement descriptionsfor those parts are omitted.

The X⁴ arithmetic circuit 83 multiplies the value expressed byExpression (11) of the shift register 83 a by X⁴. Therefore, the shiftregister 83 a has a value expressed by:a₀X⁴+a₁X⁵+a₂X⁶+a₃X⁷  (39)From the α minimal polynomial M₁(x), a relation of X⁴=X+1 is derived.Accordingly:(a₀+a₃)X⁰+(a₀+a₁+a₃)X¹+(a₁+a₂)X²+(a₂+a₃)X³  (40)Based on Expression (40), the X⁴ arithmetic section 83 through one shiftoperation performs: adding the values a₀, a₃ of the registers E₀, E₃ atthe XOR circuit 83 b ₁ and storing the sum into the register E₀; addingthe values a₀, a₁, a₃ of the registers E₀, E₁, E₃ at the XOR circuit 83b ₁, 83 b ₂ and storing the sum into the register E₁; adding the valuesa₁, a₂ of the registers E₁, E₂ at the XOR circuit 83 b ₃ and storing thesum into the register E₂; and adding the values a₂, a₃ of the registersE₂, E₃ at the XOR circuit 83 b ₄ and storing the sum into the registerE₃.

The second arithmetic section 80 b in FIG. 6 includes a first detector84 to detect error positions in the output data I₀, I₂, I₄, I₆; a seconddetector 85 to detect error positions in the output data I₁, I₃, I₅; anX-arithmetic circuit 86 to multiply the term of σ₁ by Z regarding thedata I₁, I₃, I₅; and an X²-arithmetic circuit 87 to multiply the term ofσ₂ by Z² regarding the data I₁, I₃, I₅. The output resulted from theoperation at the XOR circuit 88 and the NOR gate 89 in each detector 84,85 exhibits “1” at the error position. This output is employed to invertthe corresponding data Ii to detect 2-bit error positions in parallel atthe same time by one shift operation. The X arithmetic circuit 86 andthe X² arithmetic circuit 87 have the same arrangements as theconventional circuits shown in FIGS. 25 and 26 though they are notrequired to have registers for storing data.

(2) Second Embodiment

FIG. 7 is a block diagram showing a NAND-type flash memory according toa second embodiment, which mounts an ECC circuit on a chip.

The memory comprises eight memory cell areas 101 ₀, 101 ₁, 101 ₂, . . ., 101 ₇. Eight page buffers 102 ₀, 102 ₁, 102 ₂, . . . , 102 ₇ areprovided corresponding to the memory cell areas 101 ₀, 101 ₁, 101 ₂, . .. , 101 ₇ to temporarily store data to be written in and read out of thememory cell areas 101 ₀, 101 ₁, 101 ₂, . . . , 101 ₇. Between the pagebuffers 102 ₀-102 ₇ and I/O terminals 104 ₀, 104 ₁, . . . , 104 ₇, anECC circuit 103 is provided to generate check bits, ECC, for correctingerrors in the write data and to correct errors in the read data usingthe check bits (ECC). Different from the conventional type, for errordetection and correction, the ECC circuit 103 adds 40 check bitscommonly to information bits consisting of 528 bits×8 I/O=4224 bits data(M=528, N=8) that can be read out of and written into all memory cellareas 101 ₀-101 ₇ at a time.

Addresses and control signals, input to an I/O terminal 105, are fed toa control signal operation circuit 106 and an address decoder 107,respectively. The control signal operation circuit 106 receives variouscontrol signals, ALE, CLE, CE, WE, RE, WP, generates control voltagessupplied to various parts, and outputs a signal, READY/BUSY, to anexternal circuit. On receipt of an address from external through the I/Oterminal 105, the address decoder 107 temporarily stores it and drives acolumn decoder 108 and a block selector 109. The column decoder 108activates one column in each of the page buffers 102 ₀-102 ₇. The blockselector 109 applies a voltage to a word line in the memory cell areas101 ₀-101 ₇ required for reading, writing and erasing.

As shown in FIG. 8, each memory cell area 101 j (where j=0-7) includeselectrically rewritable, nonvolatile memory cells MC arrayed in amatrix. In this example, 16 memory cells MC are serially connected in aunit. A drain of the memory cell MC at one end is connected to a bitline BL via a selection gate transistor SG1. A source of the memory cellMC at the other end is connected to a common source line SL via aselection gate transistor SG2. Control gates of the memory cells MC inthe row direction are connected to a common word line WL. Gateelectrodes of the selection gate transistors SG1, SG2 in the rowdirection are connected to a common selection gate line SGL1, SGL2. Inthis embodiment, data of 528 bits, stored in the memory cells arrangedat odd or even numbers among 1056 memory cells MC along a control gateline, is treated as a page or a unit to be written or read at a time. Inthis example, data of 16 pages adjoining in the column direction istreated as a block or a unit to be erased at a time. In addition to1056(528×2) memory cells MC arranged along a word line WL to storeinformation bits, the memory cell area 101 ₇ is further provided withmemory cells MC to store 80(40×2) check bits for error correction.

As shown in FIG. 8, each page buffer 102 j includes 528 data storagecircuits 121. Each data storage circuit 121 is connected to two bitlines BLi, BLi+1. Data can be read out from a memory cell MC in thememory cell area 101 j via either bit line BL selected by the address. Astate of a memory cell MC in the memory cell area 101 j can be detectedvia the bit line BL. Writing into a memory cell MC in the memory cellarea 101 j can be performed when a write control voltage is applied tothe memory cell MC via the bit line BL. Among 528 data storage circuits121, either one is selected at the column decoder 108 and only theselected data storage circuit 121 is connected to the ECC circuit 103.

Therefore, in the whole memory, the data storage circuits 121 of 8 bits(8-I/O) having the same column address are connected to the ECC circuit103 by the column decoder 108. In a read operation, the memory cells MCof one page surrounded by a dashed line in FIG. 8 are selected, and dataof 528×8 bits is stored in all data storage circuits 121 at a time. Thecolumn decoder 108 increments the column address by one insynchronization with the read enable (RE) signal input from external. Asa result, one in each of the memory cell areas 101 ₀-101 ₇, eight datastorage circuits 121 in total are selected in turn and 8-bit (8-I/O)data is sequentially output to the ECC circuit 103. In a writeoperation, 8-bit (8-I/O) data is sequentially input to the ECC circuit103 from external via the I/O terminal 104 ₀-104 ₇, and the 8-bit datais sequentially output from the ECC circuit 103. The column decoder 108increments the column address by one in synchronization with the writeenable (WE) signal input from external. As a result, one in each of thememory cell areas 101 ₀-101 ₇, eight data storage circuits 121 in totalare selected in turn, and 8-bit (8-I/O) data from the ECC circuit 103 issequentially input to the selected storage circuit 121.

An ECC circuit 103 is explained next.

FIG. 9 is a block diagram showing the ECC circuit 103 in detail. The ECCcircuit 103 includes an arithmetic logic circuit 131 containing multiplestages of registers, XOR circuits and switches; a Galois arithmeticcircuit 132 for use in a syndrome computation and so forth; and an errorposition detector 133 (mainly a second arithmetic section) and a datainverter 134 operative to decode. The arithmetic logic circuit 131configures a check bit generator when the ECC circuit 103 serves as acoder, and configures mainly the syndrome arithmetic circuit and a firstarithmetic section in the error position detector when the ECC circuit103 serves as a decoder.

(2-1) Coder

In the ECC circuit 103, data is input by 8 bits (D₀-D₇) to perform errordetection and correction on a basis of data of 528×8=4228 bits. In thecase of BCH code capable of correcting 3-bit errors and detecting 4-biterrors, the following condition can be considered: the number ofinformation bits, k=4224; a code length, n=8191; the number ofcorrection bits, t=3; and m=13. Therefore, a generating polynomialrequired for coding and decoding is given below: $\begin{matrix}{{{{Fundamental}\quad{Polynomial}\text{:}{F(X)}} = {X^{13} + X^{4} + X^{3} + X + 1}}{{{Parity}\quad{{Polynomial}:{M_{0}(x)}}} = {X + 1}}{{\alpha\quad{Minimal}\quad{Polynomial}\text{:}\quad{M_{1}(x)}} = {X^{13} + X^{4} + X^{3} + X + 1}}{{\alpha^{3}\quad{Minimal}\quad{{Polynomial}:{M_{3}(x)}}} = {X^{\quad 13} + X^{\quad 10} + X^{\quad 9} + X^{\quad 7} + X^{\quad 5} + X^{\quad 4} + 1}}{{\alpha^{5}\quad{Minimal}\quad{{Polynomial}:{M_{5}(x)}}} = {X^{13} + X^{11} + X^{8} + X^{7} + X^{4} + X^{1} + 1}}\begin{matrix}{{{Generating}\quad{Polynomial}\text{:}G\quad(x)} = {M_{0}M_{1}M_{3}M_{5}}} \\{= {X^{40} + X^{39} + X^{38} + X^{35} + X^{34} + X^{33} +}} \\{X^{32} + X^{28} + X^{27} + X^{26} + X^{25} +} \\{X^{\quad 23} + X^{22} + X^{20} + X^{18} + X^{17} +} \\{X^{\quad 16} + X^{\quad 15} + X^{14} + X^{10} + X^{9} + X^{5} +} \\{X^{\quad 4} + X^{\quad 2} + X^{\quad 1} + 1}\end{matrix}} & (41)\end{matrix}$

Similar to the first embodiment, Expression (42) can be altered inExpression (43).(((((0+I₀X³⁹)X+I₁X³⁹)X+₂X³⁹)X+X₃X³⁹) . . . )X+I₅₂₇X³⁹)X  (42)(0+I₀X³⁹+I₁X³⁸+I₂X³⁷ . . . I₇X³²)X⁸+(I₈X³⁹ . . . I₁₅X³²))X⁸ . . .(I₅₂₀X³⁹+I₅₂₁X³⁸ . . . I₅₂₇X³²)X⁸  (43)

Expression (43) means the following. The data of 8 bits D₀-D₇=I₀, I₁,I₂, . . . , I₇, input by one clock of the WE signal, is multiplied on abit basis by X³⁹, X³⁸, X³⁷, . . . , x³², respectively, and each productis added into an internal register value, which is then multiplied byX⁸. Subsequently, the data of 8 bits D₀-D₇=I₈, I₉, I₁₀, I₁₅, input bythe next clock of the WE signal, is multiplied on a bit basis by X³⁹,X³⁸, X³⁷, . . . , X³², respectively, and each product is added into aninternal register value, which is then multiplied by X⁸. The sameoperations are repeated 528 times to the data of last 8 bitsD₀-D₇=I₄₂₁₆, I₄₂₁₇, I₄₂₁₈, . . . , I₄₂₂₃.

FIG. 10 shows 40-stage registers REG0, REG1, . . . , REG39 equipped inthe arithmetic logic circuit 131. These registers configure a cyclicshift register in the coder. The registers REG0, REG1, . . . , REG39have Inputs B0, B1, . . . , B39 and Outputs A0, A1, . . . , A39. Basedon the above generating polynomial (41) and Expression (43), thearithmetic logic circuit 131 executes XOR operations represented by thefollowing Expressions (45) and (46) for one data input. The XORoperations herein employed are represented by Expression (44). Prior tosending the Outputs A32-A39, the registers REG32-REG39 sends OutputsAA32-AA39, which are resulted from XOR operations as shown by Expression(45) to add 8-bit data D0-D₇ fed from external to register values.Outputs A0-31 and AA32-AA39 are led to XOR circuits. The results fromthe XOR operations, B0-B39, represented by Expression (46), are led toInputs of the registers REG0-REG39 and fetched in synchronization withthe shift register clock. When this operation is repeated 528 times, 40check bits I₄₂₂₄, I₄₂₂₅, I₄₂₂₆, . . . , I₄₂₆₄ are generated in theregisters REG0-REG39 of the arithmetic logic circuit 131.XOR3(IN1,IN2,IN3)=XOR2(XOR2(IN1,IN2),IN3)XOR4(IN1,IN2,IN3,IN4)=XOR2(XOR3(IN1,IN2,IN3),IN4)XOR5(IN1,IN2,IN3,IN4,IN5)=XOR2(XOR4(IN1,IN2,IN3,IN4),IN5)XOR6(IN1,IN2,IN3,IN4,IN5,IN6)=XOR2(XOR5(IN1,IN2,IN3,IN4,IN5),IN6)XOR7(IN1,IN2,IN3,IN4,IN5,IN6,IN7)=XOR2(XOR6(IN1,IN2,IN3,IN4,IN5,IN6),IN7)  (44)AA39=XOR2(A39,D0)AA38=XOR2(A38,D1)AA37=XOR2(A37,D2)AA36=XOR2(A36,D3)AA35=XOR2(A35,D4)AA34=XOR2(A34,D5)AA33=XOR2(A33,D6)AA32=XOR2(A32,D7)  (45)B0=XOR6(A32,A33,A35,A36,A37,A39)B1=XOR5(A32,A34,A35,A38,A39)B2=XOR2(A32,A37)B3=XOR2(A33,A38)B4=XOR6(A32,A33,A34,A35,A36,A37)B5=XOR4(A32,A34,A38,A39)B6=XOR3(A33,A35,A39)B7=XOR2(A34,A36)B8=XOR3(A0,A35,A37)B9=XOR7(A1,A32,A33,A35,A37,A38,A39)B10=XOR6(A2,A32,A34,A35,A37,A38)B11=XOR6(A3,A33,A35,A36,A38,A39)B12=XOR5(A4,A34,A36,A37,A39)B13=XOR4(A5,A35,A37,A38)B14=XOR6(A6,A32,A33,A35,A37,A38)B15=XOR6(A7,A32,A34,A35,A37,A38)B16=XOR4(A8,A32,A37,A38)B17=XOR6(A9,A32,A35,A36,A37,A38)B18=XOR4(A10,A32,A35,A38)B19=XOR4(A11,A33,A36,A39)B20=XOR7(A12,A32,A33,A34,A35,A36,A39)B21=XOR6(A13,A33,A34,A35,A36,A37)B22=XOR6(A14,A32,A33,A34,A38,A39)B23=XOR5(A15,A32,A34,A36,A37)B24=XOR5(A16,A33,A35,A37,A38)B25=XOR7(A17,A32,A33,A34,A35,A37,A38)B26=XOR5(A18,A32,A34,A37,A38)B27=XOR5(A19,A32,A36,A37,A38)B28=XOR5(A20,A32,A35,A36,A38)B29=XOR5(A21,A33,A36,A37,A39)B30=XOR4(A22,A34,A37,A38)B31=XOR4(A23,A35,A38,A39)B32=XOR5(A24,A32,A33,A35,A37)B33=XOR7(A25,A32,A34,A35,A37,A38,A39)B34=XOR4(A26,A32,A37,A38)B35=XOR6(A27,A32,A35,A36,A37,A38)B36=XOR6(A28,A33,A36,A37,A38,A39)B37=XOR5(A29,A34,A37,A38,A39)B38=XOR6(A30,A32,A33,A36,A37,A38)B39=XOR6(A31,A32,A34,A35,A36,A38)  (46)

FIG. 11 is a flowchart showing an operation of coding in the ECC circuit103 and FIG. 12 is a timing chart on coding in the same.

When a data input command (80 h) enters from external (S21), theregisters REG0-40 in the arithmetic logic circuit 131 are reset (S22),then an address (Add) is given. Subsequently, a WE (Write Enable) signalenters from external and, in synchronization with this signal, data isloaded by 8 bits into the page buffer 102 j (S23, S24, S25). At the sametime, the data is sent to the arithmetic logic circuit 131 to computecheck bits. When the column address reaches the last 528 (S25), the dataloading is terminated. Subsequently, a program command (10 h) entersfrom external, and an operation of voltage boosting by a charge pump,not depicted, is started to write data into the memory cell MC. At thesame time, prior to writing, check bits are output, using the internaloscillator and so forth, not depicted, from 40 bits REG0-REG39 by 5bytes sequentially, and stored in the data storage circuit 121 of thepage buffer 102 ₇. The data stored in the data storage circuit 121 isthen written into the memory cells MC in the page (surrounded by thedashed line in FIG. 8) selected by the external address Add.

(2-2) Decoder

{circle around (1)} Syndrome Computational Circuits

For 3-bit error correction and 4-bit error detection, four syndromes S₀,S₁, S₃, S₅ are required as it is known. The syndrome S₀ can be derivedfrom the minimal polynomial M₁(X)=X⁴+X+1. When X¹⁰=X³+1, derived fromthe minimal polynomial M₁(x)=X¹⁰+X³+1, is referred to as an a operator,the syndrome S₁ can be derived from the a operator, the syndrome S₃ froman α³ operator, and the syndrome S₅ from an α⁵ operator. Only one bitcan enter by one clock of the WE signal in the conventional decoder. Incontrast, 8-bit data can be fetched by one clock of the WE signal inthis embodiment by altering Expressions similar to the first embodimentthat alters Expression from (27) to (28), and Expression from (34) to(35). Accordingly, the syndrome S₁ can be derived from an α⁸-operator,the syndrome S₃ from an α²⁴ operator, and the syndrome S₅ from an α⁴⁰operator.

FIG. 13 shows 40-stage registers REG0, REG1, REG39 equipped in thearithmetic logic circuit 131. The register REG0 configures a cyclicshift register in the S₀ syndrome computational circuit. The registersREG1-13 configure a cyclic shift register in the S₁ syndromecomputational circuit. The registers REG14-26 configure a cyclic shiftregister in the S₃ syndrome computational circuit. The registersREG27-39 configure a cyclic shift register in the S₅ syndromecomputational circuit. The register REG0 has an Input PP0 and an OutputP0. The registers REG1-13 have Inputs AA0, AA1, . . . , AA12 and OutputsA0, A1, . . . , A12. The registers REG14-26 have Inputs BB0, BB1, BB12and Outputs B0, B1, . . . , B12. The registers REG27-39 have Inputs CC0,CC1, . . . , CC12 and Outputs C0, C1, . . . , C12. The arithmetic logiccircuit 131 executes operations shown in Expressions (47), (48), (49)and (50) based on one data input. The 8-bit data D0-D7 read out of thedata storage circuit 121 is added to the Outputs P0, A0-13, B0-13, C0-13from the registers REG0-REG39 at XOR circuits. The Outputs PP0, AA0-13,BB0-13, CC0-13 from the XOR circuits are led to the inputs of theregisters REG0-39 and fetched in synchronization with the shift registerclock. The XOR circuits connected to the registers REG1-13 configure anα⁸ arithmetic circuit, which receives the data D0-D7 input. The XORcircuits connected to the registers REG14-26 configure an α²⁴ arithmeticcircuit, which receives the data D0-D7 input. The XOR circuits connectedto the registers REG27-39 configure an α⁴⁰ arithmetic circuit, whichreceives the data D0-D7 input. In stead of the α⁴⁰ arithmetic circuit,because it has a large circuit scale, α⁴⁰ may be fed into one of inputsof the Galois arithmetic circuit 132 shown in FIG. 9, and the outputthereof and the data D0-D7 are appropriately operated at XOR circuits.

<Computation of Syndrome S₀>PP0=XOR9(P0,D7,D6,D5,D4,D3,D2,D1,D0)  (47)<Computation of Syndrome S₁>AA0=XOR2(A5,D7)AA1=XOR3(A5,A6,D6)AA2=XOR3(A6,A7,D5)AA3=XOR4(A5,A7,A8,D4)AA4=XOR5(A5,A6,A8,A9,D3)AA5=XOR5(A6,A7,A9,A10,D2)AA6=XOR5(A7,A8,A10,A11,D1)AA7=XOR5(A8,A9,A11,A12,D0)AA8=XOR4(A0,A9,A10,A12)AA9=XOR3(A1,A10,A11)AA10=XOR3(A2,A11,A12)AA11=XOR2(A3,A12).AA12=A4  (48)<Computation of Syndrome S₃>BB0=XOR5(B1,B2,B7,B9,D7)BB1=XOR7(B0,B1,B3,B7,B8,B9,B10)BB2=XOR8(B1,B2,B4,B8,B9,B10,B11,D2)BB3=XOR10(B0,B1,B3,B5,B7,B10,B11,B12,D6,D2)BB4=XOR8(B0,B4,B6,B7,B8,B9,B11,B12)BB5=XOR9(B1,B5,B7,B8,B9,B10,B12,D2,D1)BB6=XOR10(B0,B2,B6,B8,B9,B10,B11,D5,D2,D1)BB7=XOR7(B1,B3,B7,B9,B10,B11,B12)BB8=XOR8(B2,B4,B8,B10,B11,B12,D1,D0)BB9=XOR8(B3,B5,B9,B11,B12,D4,D1,D0)BB10=XOR4(B4,B6,B10,B12)BB11=XOR5(B0,B5,B7,B11,D0)BB12=XOR7(B0,B1,B6,B8,B12,D3,D0) (49)<Computation of Syndrome S₅>CC0=XOR13(C0,C1,C2,C4,C5,C7,C8,C9,C10,C11,C12, D7,D2)CC1=XOR5(C3,C4,C6,C7,D2)CC2=XOR8(C0,C4,C5,C7,C8,D4,D2,D0)CC3=XOR10(C2,C4,C6,C7,C10,C11,C12,D4,D2,D0)CC4=XOR9(C0,C1,C2,C3,C4,C9,C10,D1,D0)CC5=XOR11(C0,C1,C2,C3,C4,C5,C10,C11,D6,D4,D2)CC6=XOR12(C0,C1,C2,C3,C4,C5,C6,C11,C12,D4,D1,D0)CC7=XOR11(C1,C2,C3,C4,C5,C6,C7,C12,D3,D2,D0)CC8=XOR10(C0,C2,C3,C4,C5,C6,C7,C8,D3,D0)CC9=XOR10(C0,C1,C3,C4,C5,C6,C7,C8,C9,D0)CC10=XOR12(C1,C2,C4,C5,C6,C7,C8,C9,C10,D5,D3,D1)CC11=XOR12(C0,C2,C3,C5,C6,C7,C8,C9,C10,C11,D3,D0)CC12=XOR13(C0,C1,C3,C4,C6,C7,C8,C9,C10,C11,C12,D2,D1)  (50){circle around (1)} Error Position Detector (First Arithmetic Section)

FIG. 14 is a flowchart showing an operation of decoding in the ECCcircuit 103.

A data read command (00 h) is input, then a read address (Add) fromexternal to start reading (S31). The data of one page (528 bytes)selected by the address is read out from the memory cells MC into thepage buffers 102 ₀-102 ₇ (S32). Thereafter, in synchronization with asignal oscillated from the internal oscillator, the data D0-D7 is inputbyte by byte to the ECC circuit 103 to compute the syndrome (S33). Asshown in FIG. 27, after computations of the syndromes S₀, S₁, S₃, S₅, ifS₁=S₃=S₅=0 (S34) and if S₀=0 (S35), it is determined errorless (Normaloutput: S36). If S₀≠0 (S35), it is determined uncorrectable (S37).Unless S₁=S₃=S₅=0 (S34), computations are made for σ₂=S₁ ²S₃+S₅ andσ₀=S₁ ³+S₃ (S38). If σ₀=0 (S39) and if σ₂=0 and S₀=0 (S40), it isdetermined 1-bit error, and the control goes to an algorithm for 1-biterror correction (S41). Unless σ₂=0 and S₀=0 (S40), it is determineduncorrectable (S42). If σ₀≠0 (S39), computations are made for σ₁=S₁(S₁³+S₃) and σ₃=(S₁ ³+S₃)²+S₁(S₁ ²S₃+S₅) (S43). If σ₃=0 (S44) and if σ₂≠0and S₀=0 (S45), it is determined 2-bit errors, and the control goes toan algorithm for 2-bit error correction (S46). Unless σ₂≠0 and S₀=0(S45), it is determined uncorrectable (S47). If σ₃≠0 (S44) and if S₀=1(S48), it is determined 3-bit errors, and the control goes to analgorithm for 3-bit error correction (S49). The algorithm for 2-biterror correction is same as that for 3-bit error correction. If S₀≠1(S48), it is determined uncorrectable (S50).

FIG. 15 shows an error position detector that executes the abovecomputations. This error position detector includes a first arithmeticsection, consisting of four registers R, A, B, C of 13 bits each, andnot-depicted XOR circuits, contained in the arithmetic logic circuit131. The error position detector also includes a Galois arithmeticcircuit 132, and a second arithmetic section 133 consisting of eightlocators 141 and arithmetic circuits 142 interposed between the locators141 to operate xα, xα², xα³. 13-bit buses BUSR, BUSA, BUSB, BUSC areprovided to connect them. The output from the Galois arithmetic circuit132 is connected to the register R.

FIG. 16 shows an algorithm to compute the terms of the error positionpolynomial, σ₀, σ₁, σ₂, σ₃. The registers A, B, C store the syndromesS₁, S₃, S₅, respectively. If these syndromes are all zero, it isdetermined errorless and no operation is executed (S61). If not, anoperation is made for σ₂=S₁ ²S₃+S₅ and the operated result issequentially stored in the register R. The operated result finallyobtained is transferred from the register R to the register C (S62).Next, an operation is made for σ₀=S₁ ³+S₃ and the operated result issequentially stored in the register R. The operated result finallyobtained is transferred from the register R to the register B (S63). Ifthe operated results stored in the registers B, C are both zero, then itis determined 1-bit error (S64) and “1” is stored in the register R(S65). If not, computations are made for α₁=S₁(S₁ ³+S₃) and σ₃=(S₁³+S₃)²+S₁(S₁ ²S₃+S₅) (S66, S67, S68).

In the present embodiment, of the code length of n=8191, the informationbits of k=4224 (528×8 bits) are subjected to the error correction, whilethe information bits can have 8151 bits except for 41 check bitsoriginally in a code having the code length of n=8191. As a result, theerror position is shifted by 8151−4224+1=3928 bits. On reading from acolumn address of 0, computations are performed to multiply σ₁ by α³⁹²⁸,σ₂ by α^(7856(=3928×2)), and σ₃ by α^(3593(=3928×3−8191)) (S69, S70,S71). Similarly, on reading from a column address of i, computations areperformed to multiply σ₁ by α^(3928+i), σ₂ by α^(7858(=(3928+i)×2)), andσ₃ by α^(3596(=(3928+i)×3−8191)). Factors such as α^(3928+i) are writteninto a ROM, for example. The factor is stored in the vicinity of thecolumn data storage or in the memory cell area 101, selected by thecolumn selector 108 of FIG. 7, because it depends on the column addressof i. Alternatively, only the factor at the column address of 0 isstored and, when another address is accessed, a dummy operation ofdetecting an error position is performed to provide a matched factor.

FIG. 17 is a block diagram showing the Galois arithmetic circuit 132 indetail.

13-bit inputs A and B shown in FIG. 17A are respectively represented by:A=a ₀ X ⁰ +a ₁ X ¹ +a ₂ X ² + . . . +a ₁₂ X ¹²B=b ₀ X ⁰ +b ₁ X ¹ +b ₂ X ² + . . . +b ₁₂ X ¹²  (51)In this case, A×B can be represented by: $\begin{matrix}\begin{matrix}{{A \times B} = {A\left( {{b_{0}X^{0}} + {b_{1}X^{1}} + {b_{2}X^{2}} + \ldots + {b_{12}X^{12}}} \right)}} \\{= {{Ab}_{0} + {X\left( {{Ab}_{1} + {X\left( {{Ab}_{2} + {X\left( {{Ab}_{3} + \ldots +} \right.}} \right.}} \right.}}} \\\left. \left. \left. \left. \left. \left. \left. \left. \left. \left. \left. {X\left( {Ab}_{12} \right)} \right) \right) \right) \right) \right) \right) \right) \right) \right) \right) \right)\end{matrix} & (52)\end{matrix}$

This circuit can be configured as shown in FIG. 17B, in which A and biare subjected to the AND operation at an AND circuit 151. The operatedresult is then multiplied by X at an X multiplier 152, and the productis subjected at an XOR circuit 153 to the XOR operation with theAND-operated result from the next A and bi+1. From the a MinimalPolynomial M₁(x) in Expression (41), a relation of X¹³=X⁴+X³+X+1 ispresent. Therefore, as shown in FIG. 17C, the X multiplier 152 operatesshifting the term of X¹² into the term of X⁰; adding it into the termsof X³, X¹, X⁰ by the XOR circuit 154; and storing it in the terms of X⁴,X³, X¹.

As a result of the above operations, 13-bit registers A, B, C, D aregiven σ₁, σ₃, σ₂, σ₀ as initial values, respectively.

{circle around (2)} Error Position Detector (Second Arithmetic Section)

Error bit positions can be detected based on the following errorposition polynomial (53) in the cases of 3-bit correction and 4-bitcorrection as it is known.σ(Z)=S ₁+σ₁ ×Z+σ ₂ ×Z ²+σ₃ ×Z ³  (53)When Z=α^(I)(I=0, 1, 2, 3, . . . ) is assigned in turn to Expression(53), the position of the error can be indicated by i that holdsσ(α^(I))=0. In the present embodiment, as 8-bit data is output per WEclock, Expression (53) is altered to Expression (54), like Expression(10) is altered to Expression (38) in the first embodiment.σ(Z)=σ₀+σ₁ ×Z ⁸+σ₂ ×Z ¹⁶+σ₃ ×Z ²⁴  (54)

As a result, the error detection can be performed by 8 bitssimultaneously at every other 8 bits. In a word, of the output data of 8I/0, the error detection is performed to the I/O 0. If an error ispresent, then σ=0. As a result of the computations in FIG. 16, the13-bit registers A, B, C, D are given σ₁, σ₃, σ₂, σ₀ as initial values,respectively. The XOR circuits connected to the register A in thearithmetic logic circuit 131 configure an α⁸ arithmetic circuit. The XORcircuits connected to the register B configure an α²⁴ arithmeticcircuit. The XOR circuits connected to the register C configure an α¹⁶arithmetic circuit. The register A has Inputs AA0, AA1, . . . , AA12 andOutputs A0, A1, . . . , A12. The register B has Inputs BB0, BB1, . . . ,BB12 and Outputs B0, B1, B12. The register C has Inputs CC0, CC1, . . ., CC12 and Outputs C0, C1, . . . , C12. In this case, the α⁸, α¹⁶, α²⁴arithmetic circuits perform operations respectively represented byExpressions (55), (56) and (57):AA0=A5AA1=XOR2(A5,A6)AA2=XOR2(A6,A7)AA3=XOR3(A5,A7,A8)AA4=XOR4(A5,A6,A8,A9)AA5=XOR4(A6,A7,A9,A10)AA6=XOR4(A7,A8,A10,A11)AA7=XOR4(A8,A9,A11,A12)AA8=XOR4(A0,A9,A10,A12)AA9=XOR3(A1,A10,A11)AA10=XOR3(A2,A11,A12)AA11=XOR2(A3,A12)AA12=A4  (55)<<α¹⁶ Arithmetic Circuit>CC0=XOR4(C6 ,C7,C9,C10)CC1=XOR4(C6,C8,C9,C11)CC2=XOR4(C7,C9,C10,C12)CC3=XOR6(C0,C6,C7,C8,C9,C11)CC4=XOR5(C0,C1,C6,C8,C12)CC5=XOR4(C1,C2,C7,C9)CC6=XOR5(C0,C2,C3,C8,C10)CC7=XOR6(C0,C1,C3,C4,C9,C11)CC8=XOR6(C1,C2,C4,C5,C10,C12)CC9=XOR5(C2,C3,C5,C6,C11)CC10=XOR5(C3,C4,C6,C7,C12)CC11=XOR4(C4,C5,C7,C8)CC12=XOR4(C5,C6,C8,C9)  (56)<α²⁴ Arithmetic Circuit>BB0=XOR4(B1,B2,B7,B9)BB1=XOR7(B0,B1,B3,B7,B8,B9,B10)BB2=XOR7(B1,B2,B4,B8,B9,B10,B11)BB3=XOR8(B0,B1,B3,B5,B7,B10,B11,B12)BB4=XOR8(B0,B4,B6,B7,B8,B9,B11,B12)BB5=XOR7(B1,B5,B7,B8,B9,B10,B12)BB6=XOR7(B0,B2,B6,B8,B9,B10,B11)BB7=XOR7(B1,B3,B7,B9,B10,B11,B12)BB8=XOR6(B2,B4,B8,B10,B11,B12)BB9=XOR5(B3,B5,B9,B11,B12)BB10=XOR4(B4,B6,B10,B12)BB11=XOR4(B0,B5,B7,B11)BB12=XOR5(B0,B1,B6,B8,B12)  (57)

FIG. 18 is a circuit diagram showing a specific arrangement of thelocator 141. The locator 141 includes XOR circuits 161 and NOR circuits162 to compute σ(Z) and outputs “H” if an error is present (σ=0) at theI/O 0 (j=1-7). As a result, the data inverter 134 of FIG. 9 inverts thedata from the data storage circuit 121 in the page buffer 102 ₀ andoutputs the inverted data. Alternatively, as indicated by a dashed arrow135 in FIG. 9, error correction can be directly performed to the data atthe error position in the page buffer 102.

On the other hand, the data at the I/O 1 has values in σ(Z) with theterm of σ₁ multiplied by Z, the term of σ₂ multiplied by Z², and theterm of σ₃ multiplied by Z³. Accordingly, as shown in FIG. 15, anarithmetic circuit 142 ₁ is mounted to operate the term of σ₁×X, theterm of σ₂×X², and the term of σ₂×X³, and supplies the output to thelocator 141 ₁ to solve the error position polynomial. If an error isdetected (σ=0), the output comes to “H”. When these X, X², X³ arithmeticcircuits are assumed to have Inputs X0-X12 and Outputs Y0-Y12, thearithmetic circuits execute the following operations. The arithmeticcircuits are not required to have registers to store data.

<X Arithmetic Circuit>Y0=X12Y1=XOR2(X0,X12)Y2=X1Y3=XOR2(X2,X12)Y4=XOR2(X3,X12)Y5=X4Y6=X5Y7=X6Y8=X7Y9=X8Y10=X9Y11=X10Y12=X¹¹  (58)<X² Arithmetic Circuit>Y0=X11Y1=XOR2(X11,X12)Y2=XOR2(X0,X12)Y3=XOR2(X1,X11)Y4=XOR3(X2,X11,X12)Y5=XOR2(X3,X12)Y6=X4Y7=X5Y8=X6Y9=X7Y10=X8Y11=X9Y12=X10  (59)<X³ Arithmetic Circuit>Y0=X10Y1=XOR2(X10,X11)Y2=XOR2(X11,X12)Y3=XOR3(X0,X10,X12)Y4=XOR3(X1,X10,X11)Y5=XOR3(X2,X11,X12)Y6=XOR2(X3,X12)Y7=X4Y8=X5Y9=X6Y10=X7Y11=X8Y12=X9  (60)

The data at the I/O 2 has values in σ(Z) with the term of σ₁ multipliedby Z², the term of σ₂ multiplied by Z⁴, and the term of σ₃ multiplied byZ⁶. If arithmetic circuits are mounted to operate the term of σ₁×X², theterm of σ₂×X⁴, and the term of σ₂×X⁶ on the basis of I/O 0, thearithmetic circuit for a large multiplication such as X⁶ increases thecircuit scale. Therefore, in this embodiment, an arithmetic circuit 141₁ is provided to multiply the output from the arithmetic circuit 141 ₂by ×X, ×X², ×X³ again. Similarly, arithmetic circuits are provided up to141 ₇ corresponding to the I/O 7.

If there is a problem on a signal transmission time delay, the eightlocators 141 configuring the error position detector (second arithmeticsection) 133 may be divided in two groups of four locators, as shown inFIG. 19, which are arranged on both sides of the arithmetic logiccircuit 131. This arrangement is effective to halve the signaltransmission path to the locator 141.

FIG. 20 is a timing chart on decoding in the ECC circuit 103. FIG. 20Ashows data reading and error correcting after computations of all termsin the error position polynomial.

When a data read command (00 h) is input from external, followed by aread address (Add), a READY/BUSY signal is activated to start reading.First, the data of one page (528 bytes) selected by the address is readout from the memory cells MC into the page buffers 102 ₀-102 ₇. Then, insynchronization with a signal oscillated from the internal oscillator,the data D0-D7 is input byte by byte to the ECC circuit 103 to computethe syndromes and operate the terms of the error position polynomialusing the computed syndromes S₀, S₁, S₃, S₅. Thereafter, the data isread out in synchronization with the write enable (RE) signal and theerror correction is executed at the same time. In this case, compared tothe absence of the ECC circuit 103, an additional busy time is derivedfrom a computation time for syndromes plus a computation time for errorcorrection operators in total. For example, if one syndrome computationrequires 50 ns and an arithmetic time for an operator is equal to 3.6μs, then 528×50 ns+3.6 μs=30 μs.

FIG. 20B shows an example of computing the syndromes S₀, S₁, S₃, S₅ atthe same time of data reading. After the reading is started similarly,the data of one page (528 bytes) is read out from the memory cells MCinto the page buffers 102 ₀-102 ₇. Then, the data is output from thepage buffers 102 ₀-102 ₇ byte by byte in synchronization with the REsignal and the ECC circuit 103 computes the syndromes. As a result ofthe syndrome computation, if an error is detected, a status fail command(70 h) is activated. Accordingly, an operator for error correction iscomputed and the data is output again to correct the error. In thiscase, if no error is present, an additional busy time in total is equalto zero.

As for 2-bit error correction and 3-bit error detection, the number ofpermissible random failures (the number of random failures at a devicefailure probability of 1 ppm) is naturally better in the case of 528information bits than in the case of 4224 information bits. Table 1shows an application to a 256 Mb NAND-type flash memory.

From Table 1, the number of permissible random failures is 100 bits at2-bit correction BCH code for 528 information bits, and only 30 bits for4224 information bits. To the contrary, at 3-bit correction BCH code for4224 information bits, the random failures can be permitted up to 300bits with a necessary code as short as 40 bits. Further, at 4-bitcorrection BCH code for 4224 information bits, the random failures canbe permitted up to 1000 bits with a necessary code as short as 53 bitseffectively. TABLE 1 Number of random failures in 256 Mb at Devicefailure probability of 1 ppm Code length per Number of Page (528B)Failures 2-bit correction BCH code 21 × 8 = 168 bits 100 bits (528information bits) 2-bit correction BCH code 27 bits  30 bits (4224information bits) 3-bit correction BCH code 40 bits 300 bits (4224information bits) 4-bit correction BCH code 53 bits 1000 bits  (4224information bits)

Table 2 shows chip sizes of NAND-type flash memories of 128 M-bits and512 M-bits when no ECC circuit is mounted, compared with those when theconventional 2-bit correction ECC circuit is mounted, and those when the2-bit correction ECC circuit of the present embodiment is mounted. TABLE2 128M (0.16 μm) 512M (0.16 μm) No ECC circuit 41.88 mm² (100.0%) 136.99mm² (100.0%) ECC circuit mounted 44.72 mm² (106.8%) 143.96 mm² (105.1%)(Conventional) ECC circuit mounted 43.21 mm² (103.2%) 140.42 mm²(102.5%) (Embodiment)

Thus, the flash memory with the conventional ECC circuit mounted thereonhas an increase in chip size of 6.8% (128M) and 5.1% (512M). To thecontrary, the flash memory with the ECC circuit of the presentembodiment mounted thereon has an increase in chip size of 3.2% (128M)and 2.5% (512M), which is half the conventional one.

As obvious from the forgoing, the information bits are generated perM-bit that is a unit for accessing each memory area in the art. To thecontrary, according to the embodiments of the invention, N bits can beprocessed in parallel. Therefore, it is possible to allocate a set ofcheck bits to M×N bits and reduce the number of check bits in totalrelative to the number of information bits. This is effective to improvea chip integration density while mounting an on-chip error correctioncircuit.

Having described the embodiments consistent with the invention, otherembodiments and variations consistent with the invention will beapparent to those skilled in the art. Therefore, the invention shouldnot be viewed as limited to the disclosed embodiments but rather shouldbe viewed as limited only by the spirit and scope of the appendedclaims.

1-15. (canceled)
 16. A semiconductor device, comprising: A pieces ofmemory cell areas, each of which includes a plurality of memory cellsarrayed in a matrix; and an error correction circuit including a coderconfigured to generate check bits for error correcting and to attachsaid check bits to data to be written into said memory cell area and adecoder configured to process for error correcting said data read outfrom said memory cell area with said generated check bits. said errorcorrection circuit treats K=B×A bits (where B denotes a natural number)as an information bit length, generates one H bit check bits for saidinformation bit length, and treats (K+H) bit data as a unit to bewritten or read at a time.
 17. The semiconductor device according toclaim 16, wherein said decoder comprises: a syndrome computationalcircuit configured to compute a syndrome from said information bits andsaid check bits input; an error position detector having a firstarithmetic section configured to compute a term in an error positionpolynomial from said computed syndrome, and a second arithmetic sectionconfigured to compute an error position polynomial from said computedterm in said error position polynomial and detect an error position; anda data inverter configured to conduct a data inversion process for dataread out from said memory cell area at said error position detected. 18.The semiconductor device according to claim 17, wherein said coder, saidsyndrome computational circuit and said first arithmetic section areconfigured by switching registers and arithmetic circuits contained inan arithmetic logic circuit.
 19. The semiconductor device according toclaim 17, further comprising a Galois arithmetic circuit employed tocompute said syndrome or said term in said error position polynomial.20. The semiconductor device according to claim 17, wherein said secondarithmetic section including a plurality of locators and a plurality ofarithmetic circuits each connected between said locators, and whereinsaid first arithmetic section is connected to said second arithmeticsection with a plurality of buses.
 21. The semiconductor deviceaccording to claim 17, wherein said second arithmetic section isarranged dividedly on both sides of said first arithmetic section.
 22. Asemiconductor device comprising an error correction circuit including acoder configured to generate check bits for error correcting and toattach said check bits to data, wherein said coder attaches one H bitcheck bits to information bit data of K=B×A bits (where B denotes anatural number).
 23. A semiconductor device comprising an errorcorrection circuit including a decoder configured to process data forerror correcting with check bits, said decoder comprising: a syndromecomputational circuit configured to compute a syndrome receiving inputof (K+H) bit data generated by attaching one H-bit check bits toinformation bit data of K=B×A bits (where B denotes a natural number)per A-bit; an error position detector having a first arithmetic sectionconfigured to compute a term in an error position polynomial from saidcomputed syndrome, and a second arithmetic section configured to computean error position polynomial from said computed term in said errorposition polynomial and detect an error position, and a data inverterconfigured to conduct a data inversion process for said data at saiderror position detected.
 24. The semiconductor device according to claim23, wherein said second arithmetic section including a plurality oflocators and a plurality of arithmetic circuits each connected betweensaid locators, and wherein said first arithmetic section is connected tosaid second arithmetic section with a plurality of buses.
 25. Thesemiconductor device according to claim 23, wherein said secondarithmetic section is arranged dividedly on both sides of said firstarithmetic section.